1. Technical Field
The present invention relates to circuit design and more particularly to a system and method for memory element characterization in latch-type circuits.
2. Description of the Related Art
Latch-type circuits are employed in many electronic applications. The design of a latch circuit is an important aspect of the circuit's performance. The characterization of latch-type circuits is particularly tedious, however.
Latch characterization is typically based on circuit simulation experiments, mainly using transient analysis. In contrast to other characterization targets for library elements, e.g., propagation delay, there are no simulation experiments that can directly determine the set-up or hold-time of a latch.
Instead, a sequence of simulations with varying time delays between clock and data transition events are typically performed, essentially, in a search procedure for the situation when the settling time of the internal latch starts degrading. As a consequence, the characterization of the latch library elements becomes a very costly and disproportionately large portion of the total characterization effort.